1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to a system and method for efficiently characterizing memory compilers.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, non-volatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that various parameters such as delay, access time, cycle time, etc., are significant factors in designing a high performance memory instance, whether provided as a stand-alone device or in an embedded application. In order to ensure that a compilable memory circuit operates in accordance with its performance specifications, the memory compiler used for compiling the memory instance is typically required to be thoroughly characterized in terms of the various parameters of interest. Typically, timing parameters such as cycle time (tcc), clock-to-Q delay or access time (tcq), et cetera, are extensively simulated for a memory compiler during its design phase.
The high-density memory compilers of today are operable to compile memory instances of various aspect ratios (i.e., height and width of the floor plan of a memory array having a select number of physical rows and a select number of physical columns, which are organized using a particular column multiplex (MUX) factor). Accordingly, when a family of compilers designed for memory instances having a variable number of rows or columns need be characterized, each particular compiler that corresponds to an instance needs to be characterized with respect to several key parameters.
As is well known, the high-density compilers are typically comprised of multiple clusters (depending on leaf cell hierarchy) that represent circuit/area optimization schemes for a combination of words, bits per word (BPW), and MUX factors, which ultimately translates into certain rows and columns. The array of data bits can range vastly, for example, rows and columns each ranging from 8 to 1024. A memory compiler is associated with each instance of a particular row/column combination and all such memory compilers within a compiler family need to be characterized to obtain relevant parametric data, for example, timing data which is encapsulated in a timing estimator. It should be appreciated by those skilled in the art that the task of creating parametric datasets large enough to cover the entire applicable range of compilers is very processor-intensive, requiring tens of hundreds of hours in CPU time.
Furthermore, parametric data thus obtained must satisfy stringent levels of accuracy. That is, the memory compilers' parametric data generated via characterization must be within a narrow range of the actual data obtained for the corresponding memory instances. Typically, it is expected that the memory compilers' parametric data should be within 2–3% of the actual data in order to be satisfactory.
State-of-the-art solutions relating to memory compiler characterization typically involve simulation of an extensive number of memory compilers to obtain data points with respect to a particular parameter of interest. An estimator is used subsequently to estimate the data for the remaining memory compilers of a compiler family. Although such techniques have been widely implemented, they are not efficient in general. For example, a huge number of memory compilers still need to be characterized in order that the estimated data is within a specified error rate of 2–3%. As a consequence, large amounts of processor time and engineering resources continue to be required for adequately characterizing the state-of-the-art memory compilers.
In addition, where migration to a different family of compilers is necessitated due, for example, to a change in the MUX factor, adaptation of a different technology, et cetera, an entirely new set of memory compilers needs to be characterized to the same exacting standards again. Clearly, the requirement to create large enough datasets necessary for adequate characterization each time simply compounds the deficiency of the existing solutions.